SCEC 2017

Overview

Supercomputing or High Performance Computing (HPC) platforms are used to power discoveries and to reduce the time-to-results in a wide variety of disciplines (such as, astrophysics, archaeology, and financial trading). For optimally utilizing these high-end platforms, it is critical to have scalable and efficient software (applications, middleware, libraries, and tools) that can take advantage of the innovative hardware features in these platforms. However, developing and maintaining HPC software remains a challenging task because the HPC platforms for which they are developed typically have a short life-span, and are replaced with next generation platforms within a few years. As we progress towards the exascale computing era, the task of developing and maintaining HPC software is likely to become even more challenging than now due to the increasing complexity of the HPC platforms and the pressing need for power-efficiency and memory usage optimization. There is a potential of mitigating some of the challenges related to developing HPC software for the current and future generation systems by adopting the innovations in the advanced software engineering sub-disciplines, such as model-driven engineering, generative programming, and adaptive and reflective software systems.


The goals of the first workshop on “Software Challenges to Exascale Computing” are to foster international collaborations across the HPC and the advanced software engineering disciplines, and to exchange knowledge on the challenges and solution strategies for developing scalable and efficient HPC software. The workshop attendees will learn about the state-of-the-art and the state-of-the-practice in the areas of HPC software development and advanced software engineering through presentations, hands-on sessions, and open-discussion sessions. Those already skilled in the advanced software engineering discipline will learn about the challenges and opportunities in the HPC domain, and can find interesting test cases for generalizing their innovative approaches.

Overview

The workshop will provide a forum through which hardware vendors and software developers can communicate with each other and influence the architecture of the next generation supercomputing systems and the supporting software stack. By fostering cross-disciplinary associations, the workshop will serve as a stepping stone towards innovations in the future.

Benefits to the researchers and users in the academia: disseminate your results to the public, and find potential collaborators.

Benefits to software developers: understand the future trends in the HPC hardware and develop collaborations in the code modernization and optimization disciplines.

Benefits to HPC service providers: understand the challenges that the community faces in using the HPC platforms efficiently, and connect with the user-community.

Benefits to HPC hardware vendors: understand the evolving needs of the HPC community, and network with potential customers.

Benefits to students: network with HPC and advanced software engineering professionals and researchers, learn about internship and career opportunities, discuss the opportunities for higher education.


Topics of interest include, but are not limited to:

  • Best practices for HPC software development
  • Software support for HPC in the cloud
  • Supporting software and middleware for HPC environments
  • Techniques for developing power-efficient applications
  • Software tools for HPC code modernization and optimization
  • Design and development of adaptive and reflective systems
  • Innovations in efficient utilization of memory hierarchies on HPC platforms
  • High-level interfaces, libraries, compilers, and runtime systems for parallel programming
  • Application of generative programming and model-driven engineering techniques for solving large-scale problems


Tentative Agenda (Subject to Change)


Time
Topic
Speaker

09:00-09:30
Registration, badges, kit-bag pick-up
Location: TBD

09:30-10:00
Welcome to the workshop - overview & goals
Ritu Arora, TACC/ Sharda Dixit, C-DAC
Welcome from C-DAC
Hemant Darbari, C-DAC

10:00-10:25
A User-Defined Code Transformation Approach to Separation of Performance Concerns
Hiroyuki Takizawa, Tohoku University


Takizawa Picture


Bio:
Hiroyuki Takizawa is currently a professor of Cyberscience Center, Tohoku University. His research interests include performance-aware programming, high-performance computing systems and their applications. Since 2011, he is leading a research project, supported by JST CREST, to explore an effective way of assisting legacy HPC code migration to future-generation extreme-scale computing systems. He received the B.E. Degree in Mechanical Engineering, and the M.S. and Ph.D. Degrees in Information Sciences from Tohoku University in 1995, 1997 and 1999, respectively.

Abstract: Today, high-performance computing (HPC) application codes are often optimized and specialized for a particular system configuration to exploit the system's potential. One severe problem is that simply modifying an HPC application code often results in degrading the performance portability, readability, and maintainability of the code. Therefore, we have been developing a code transformation framework, Xevolver, so that users can easily define their own code transformation rules for individual cases, in order to express how each application code should be changed to achieve high performance. In this talk, I will briefly review the Xevolver framework and introduce some case studies to discuss the benefits of the user-defined code transformation approach.


10:25-10:50
Talk-2
Vipin Chaudhary, NSF

10:50-11:15
COFFEE BREAK & NETWORKING

11:15-11:40
Technologies for Exascale Computing
Nash Palinaswamy, Intel


Dr. Nash Palaniswamy's Picture


Bio:
Dr. Nash Palaniswamy has been at Intel since October 2005, and focuses in the area of Enterprise and High Performance Computing in the Datacenter group. He is currently the Senior Director for Worldwide Solutions Enablement and Revenue Management for Enterprise and HPC. In this role, he is responsible for managing all strategic opportunities in Enterprise and HPC and managing and meeting revenue for the Enterprise and Government segment in Intel’s datacenter group. Dr. Palaniswamy leads a team that drives strategic opportunities worldwide (solutions, architecture, products, business frameworks, etc) in collaboration with Intel’s ecosystem partners.

His prior responsibilities at Intel included being the lead for worldwide business development and operations for Intel® Technical Computing Solutions, Intel® QuickAssist Technology based accelerators in HPC, and World Wide Web Consortium Advisory Committee representative from Intel. Prior to joining Intel as part of the acquisition of Conformative Systems, an XML Accelerator Company, he has served in several senior executive positions in the industry including being the Director of System Architecture at Conformative Systems, CTO/VP of Engineering at MSU Devices (a publicly traded company), and Director of Java Program Office and Wireless Software Strategy in the Digital Experience Group of Motorola, Inc.

Dr. Palaniswamy holds a B.S. in Electronics and Communications Engineering from Anna University (Chennai, India) and an M.S. and Ph.D. from the University of Cincinnati in Electrical and Computer Engineering.

Abstract: Intel is investing in a broad set of technologies to move computing to the address the challenges of Exascale computing. These technologies are targeted to reach next generation performance in a configurable system that can achieve exceptional performance in data analytics, traditional high performance computing and artificial intelligence. Being able to address all of these application domains is of critical importance.

Intel is investing in processors, fabric, memory and software. Each will be discussed along with their respective importance in achieving Exascale.


11:40-12:05
Talk-4
Aniruddha Gokhale, Vanderbilt University

12:05-12:30
The EX Factor in the Exascale Era: Factors driving changes in HPC
Bharatkumar Sharma, Nvidia


Takizawa Picture


Bio:
Bharatkumar Sharma obtained master degree in Information Technology from Indian Institute of Information Technology, Bangalore. He has around 10 years of development and research experience in domain of Software Architecture, Distributed and Parallel Computing. He is currently working with Nvidia as a Senior Solution Architect, South Asia. He has published papers and journal articles in field of Parallel Computing and Software Architecture.

Abstract: GPU’s has been used to accelerate HPC algorithms which are based on first principles theory and are proven statistical models for accurate results in multiple science domains. This talk will provide insights into the HPC domain and how it affects the programs you write today and in the future in various domains.


12:30-13:30
LUNCH BREAK

13:30-13:55
Talk-6
VCV Rao, C-DAC

13:55-14:15
High-Productivity Tools for Code Modernization and Migration to Future Generation Supercomputing Platforms
TBD

14:15-15:15
Multiple Lightning Talks
TBD

15:15-15:30
COFFEE BREAK & NETWORKING

15:30-17:00
Hands-on session: Using the Interactive Parallelization Tool (IPT) to Generate OpenMP, MPI, and CUDA Programs
Ritu Arora, TACC

17:00-17:30
Parallel programming contest (MPI/OpenMP/CUDA) - parallelize programs with or without IPT - C/C++ as the base language - prizes for top contestants - The winner award is Nvidia Tesla K40C GPU

17:30-18:00
Panel Discussion
TBD

18:00-19:00
NETWORKING RECEPTION AND PRIZE WINNER ANNOUNCED


Important Dates

  • Registration opens on: November 1, 2017
  • Abstract Submission Deadline: November 15, 2017 (original), November 20, 2017 (extended)
  • Acceptance Notification: November 25, 2017
  • Registration closes on: December 1, 2017
  • Final submission deadline: December 7, 2017
  • Workshop will be held on: December 17, 2017


Committee

Workshop Chairs


Publicity

  • Nitin Sukhija, Slippery Rock University of Pennsylvania, USA
  • V Venkatesh Shenoi, Centre for Development of Advanced Computing, India

Program Committee

  • Amarjeet Sharma, Centre for Development of Advanced Computing, India
  • Amit Majumdar, San Diego Supercomputing Center, USA
  • Anil Kumar Gupta, Centre for Development of Advanced Computing, India
  • Antonio Iglesias Gomez, Oak Ridge National Laboratory, USA
  • Carlos Rosales Fernandez, Intel, USA
  • Lars Koesterke, Texas Advanced Computing Center, USA
  • Rekha Singhal, Tata Consultancy Services, India
  • Sandeep K Joshi, Centre for Development of Advanced Computing, India
  • Saumil Merchant, Shell, India
  • Shreya Bokare, Centre for Development of Advanced Computing, India
  • Soham Ghosh, Centre for Development of Advanced Computing, India
  • Suman Roychoudhury, Tata Consultancy Services, India
  • VCV Rao, Centre for Development of Advanced Computing, India
  • Vinodh Kumar M, Centre for Development of Advanced Computing, India

Webmaster




Current Sponsors


Sponsorship Levels

  • Platinum Level:
    US $7000, one speaker-slot, large-sized logo in the header area of the website, name displayed prominently on the signage in workshop area, promotion through workshop advertisements, 10 complimentary registrations, URL to the sponsor website added to the workshop website, up to ten products and services highlighted through blogs on the workshop forum page, invitation on a panel

  • Gold Level:
    US $5000, medium-sized logo on the website, signage in workshop area, promotion through workshop advertisements, up to five products and services highlighted through blogs on the workshop forum page, invitation on a panel, 5 complimentary registrations

  • Silver Level:
    US $3000, logo on the website, promotion through workshop advertisements, one product or service highlighted through a blog on the workshop forum page, 3 complimentary registrations

  • Bronze Level:
    US $2000, logo on the website, promotion through workshop advertisements, 2 complimentary registrations

CFA (Call For Abstracts)


The SCEC workshop will include a track for lightning talks during which ten-minute talks will be presented in a sequence. The talks will provide a high-level overview of the topics that are aligned with the theme of the workshop. While the time allocated for the lightening talks may not be enough for presenting the fine details of the chosen topic, it could be enough for including key information that piques the interest of the audience for an engaging discussion after the talk. The abstract and slides of the talks will be published on the workshop website. There can be multiple authors on a submission but only one presenter is permitted for each lightning talk due to time-constraints.

Guidelines for preparing the submission for the lightning talk are as follows:

In maximum 300 words, the abstract should answer the following questions on a topic that is relevant to the workshop:


A rough draft of the proposed presentation (up to 5 slides) should also be submitted along with the abstract. The abstracts and the slides must be submitted in the PDF format through the submission system at the following URL: https://easychair.org/conferences/?conf=scec17

*Abstracts will not be accepted over email. Abstracts which are incomplete or received after the deadline will not be considered. The submission system will close on November 20, 2017.


Presentation guidelines:

Lightning talk presentations are limited to one per speaker. Co-authors are not included in this rule. A person can be a co-author on any number of abstracts.

Registration

The registration fees for the workshop is Rupees 1000 (US $16) and can be paid at the venue using cash or credit/debit card. This fees will be used to offset the cost of food and beverages that will be offered at the venue. All the workshop attendees should register in advance by filling the following form:


Workshop Venue

Hotel Royal Orchid

Opposite to BSNL Office, Near Durgapura Flyover, Tonk Road, Durgapura, Jaipur Rajasthan India 302018

Contact

For any questions regarding the workshop, please contact us at: scecforum@gmail.com